1. Field of the Invention
The present invention relates to photomasks and photolithographic patterning in the production of integrated circuits.
2. Photolithography Background
Photolithography, is an optical printing and fabrication process by which features on a photomask are imaged and defined onto a photosensitive layer coating a substrate. The photomask may be used to generate the same master pattern on many locations on a given substrate as well as on many substrates. Photolithography and photomasks are critical to the efficient manufacture of integrated circuits (ICs) and to the progression of the IC industry.
A typical photolithography imaging system, often referred to as a ‘stepper’ or a ‘scanner’ in two common implementations, is used to project the image of the photomask onto the substrate. The substrates are typically, but not limited to, silicon wafers for integrated circuit (IC) manufacturing applications. The image from the mask and stepper exposes a photosensitive layer, or photoresist which, following development, results in a physical relief image in the photoresist. The resulting relief image is typically used as an in-situ mask itself by other subsequent fabrication processes to define the various individual material layers or regions comprising an IC through physical-chemical processes and actions such as etching, material deposition, or ion-implantation of dopants.
For IC fabrication applications, photomask features correspond to the various base physical IC elements which comprise functional circuit components such as transistors, and interconnect wires, contacts, and vias as well as other elements which are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes.
Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process a large number of material layers of various shapes and thicknesses and with various conductive and insulating properties may be built up to form the overall integrated circuit. The photolithography process generally follows IC design and photomask fabrication.
IC Design
An IC design often requires an immense effort and highly specialized electronic design automation tools (EDA) such as from Cadence Design Systems, Inc. Design information generated by tools and designer activity is captured in files or databases and includes, depending upon the type of circuit; functional descriptions, electronic schematics, results of timing and power analyses, as well as the geometrical layout of the various features shapes comprising the IC. To facilitate design reuse and speed up the overall IC design cycle, typically pre-existing and pre-characterized circuit design component elements in the form of library cells, macro-cells, or blocks are often used. The IC physical design typically includes and describes each layer required to manufacture the IC in the fabrication facility (fab) using a photolithographic process.
For example a ‘gate’ layer is typically associated with the gate photomask and the photolithographic patterning (and subsequent pattern definition such as through reactive ion etching) of the polysilicon transistor gates. Similarly, a ‘contact’ or ‘via’ layer corresponds to a contact or via mask and typically corresponds to patterning the interconnect contacts with active transistors, metal wires, or other devices comprising the IC. An IC physical design may be comprised of more than 25 layers.
IC Design Database
Typically, design data exists in many separate files including physical, logical, and various functional data which are often unique to the individual design tool being used. For example, the physical design is often stored in a GDS-II stream formatted file. GDS-II is a file format which is classified as a “data interchange format,” used for transferring mask-design data between the IC design and the fabrication facility. It is an EDA industry standard file format. The electronic network or schematic is often stored as a net list file. However there are many files for each of the diverse requirements of the design flow and often a number of the files are proprietary to one vendor and unusable by another vendor's tool. Recognizing this problem, the industry is making significant strides towards broad implementation of a consistent and standard open source database enabling the efficient storage, management, and dynamic access of IC design and manufacturing data as well as interoperability of design tools. An example is the OpenAccess database for design and the Universal Data Model (UDM) for manufacturing and the design-manufacturing interface.
Photomasks
Following IC design, photomasks (also referred to as reticles or simply ‘masks’) are created from the physical design or layout. The mask provides the master image of a specific layer of the physical layout, and as such, are critical to the lithography process. The accuracy with which masks are fabricated and the manner in which they are integrated with the design and lithographic system parameters greatly impacts the performance and yield of the resulting IC's manufactured.
Masks may be created by various processes. In one method, an electron beam system is used in a lithographic process to write the pattern onto a photoresist-coated glass mask substrate in accordance with mask data derived from a physical design layout. Optical laser-based systems, typically in the deep ultraviolet, are also used similarly. Following development of the exposed photoresist, the resulting relief mask is used as an in-situ mask for the etching of the chrome or other mask material resulting in an optical transmission mask usable in a photolithography system.
Today the features on the mask, when normalized to the reduction ratio of the projection lithography system, are often significantly smaller than the exposure illumination wavelength of the system. Imaging subwavelength features onto the substrate is a significant challenge even if various sophisticated resolution enhancement techniques are used. The result is in poor light/dark image contrast between the features desired to be printed and those that are not and distortion in the printed features in comparison to the designer's ‘target layout.’ Despite resolution enhancement efforts, distortions of the printed features may persist in comparison with the designer's desired target layout.
There are various and different types of masks and different styles of resolution enhancement technology (RET) techniques typically used to mitigate subwavelength effect distortions and to improve the resolved feature process latitude. Mask types include conventional chrome on glass masks, masks which additionally include phase shifting features, chromeless or phase only masks, and so on. RETs include attenuated phase-shifting masks (attPSM) and alternating aperture phase-shifting masks (altPSM), aggressive model-based simulation-driven optical proximity corrected (OPC) masks, rules-based OPC masks, scattering bar (or sub-resolution assist feature (SRAF), masks and so on. All RETs, in this sense, involve artificial optical enhancement features which are not a part of the physical circuit. The physics and action of the photolithographically printed enhanced resolution circuit features can be quite complex to non-specialists and is typically highly non-intuitive, particularly to non-lithographers. Furthermore, the proper application of RETs typically requires sophisticated optical models, large amounts of numerical simulation, and specialized personnel.
PSM masks typically require definition of multiple materials and a more complex manufacturing sequence than conventional chrome-on-glass (COG) mask technology. This involves a number of sequential mask writing and etch processes of each of the various materials/layers to the appropriate specification to achieve the required mask property. For example, for some alternating aperture PSM (altPSM) masks, not only is the chrome layer etched but the glass itself is etched to provide two or more different phase shifting regions. The chrome and phase shifting regions furthermore may exist in a number of configurations. In one configuration, shown later in the examples, the altPSM mask is a single exposure mask wherein the chrome is etched to provide an amplitude transmission mask and the glass is etched to specific depths to provide conjugate phase shifters. This configuration is not typically used however. In a more common configuration, the altPSM masking is performed using two masks and two exposures; a conventional chrome mask as well as a purely phase shifter mask used in two separate lithographic exposures of a common photoresist.
Masks are typically fabricated at a scale of up to 5× magnification of the final patterned image size and corresponding to the reduction ratio of the projection imaging system.
Photomask Data
In typical applications, the design layout data must be formatted appropriately for the mask fabrication equipment. The polygonal shapes of the design layout are typically fractured into a data set of simple base polygons appropriate for the mask writing equipment. These data typically reside in various files and are often specific to particular vendor equipment and may exist in proprietary vendor formats. These data files typically do not contain any design knowledge per se, but are primarily the aggregation of machine-oriented base polygons which comprise the mask layer and which correspond to the mask writer to be used.
Similarly, photomask inspection data resides in a different file formats however the data in effect comprises a template describing the acceptable shape including acceptable shape variations following mask fabrication. Typically the photomask data files can be huge, and the sheer volume of data and data transfer throughout the systems involved in mask fabrication can impact the available efficiencies of the mask fabrication cycle as the data are unordered and non-prioritized. One example of a photomask file format used for mask writing is MEBES, (Manufacturing Electron Beam Engraving System.)
Photomask Defects
Before being used in a photolithography system to replicate the mask image in reduced size onto a wafer when building the IC, the mask is inspected for defects. A defect is typically considered to be any deviation from the ideal physical layout defined by the IC designer outside of an acceptable margin or tolerance. Defects found in the mask will often be repaired so that they will not be replicated and introduce harmful distortions to the chips created from that mask. However defect repair is difficult and time consuming and indeed may even cause more harm than good due added and complex processing and handling. So it is important to waive defects if possible and to ascertain the repair costs of any perceived defects to ascertain whether the repair is worth it.
Some defects may be waived if the product engineer ascertains that impact is negligible. However determining a given defect's potential impact and criticality is often ambiguous or very time intensive. With the exception of gross defects, many defects are poorly correlated with a functional outcome.
Subwavelength lithography further complicates correlating defects with functional results. Since many features are inherently distorted, defect screening based upon traditional, rather simple, uniform ‘visual’ criteria is increasingly difficult. Furthermore the size of a defect on a photomask is not necessarily an indicator of the relative impact on the resulting silicon pattern due to the highly non-linear nature of subwavelength photolithography. Compounding this difficulty is the fact that the defect will impact various physical features of the same size and shape on the wafer very differently depending upon device or process context. For example, a given distortion of a shape used as a switching transistor gate may be unacceptable whereas the same distortion and shape in the context of a long interconnect may be wholly insignificant. The same can be said of other cases, for example, low-power versus high-speed transistors.
With current technology, IC photomask defect interpretation requires highly skilled multidisciplinary interpretation of the potential impact on the IC and attempts to waive defects based upon overly simplistic ‘visual’ metrics unrelated to specific device performance or yield. However, defect review is often ineffective and overly burdensome as the circuit context of the features impacted is typically not known and the interpretation of the resultant distortions on the final IC is often highly non-intuitive due to the increasingly complex non-linear lithography and device (or other) physics in-play.
Resolution enhancement technology (RET) features add to the difficulty as they are, at least in the case of OPC (optical proximity corrected), predistortions of the target layout designed to achieve the proper silicon pattern shape. These RET features may themselves be distorted due to the various limitations of the mask writing process including grid snapping and temporal or thermal variations. Under some circumstances of distortion, the RET feature may be worse than nothing at all. Similarly, some distortions sitting within a natural RET-like zone may conceivably even be beneficial. Therefore the simple visual metrics historically applied uniformly to all features have significant drawbacks.
The goal for mask writing is to pattern the photomask in a manner such that the features will be within acceptable distortion margins resulting in a photolithographically printed pattern that has sufficient fidelity across an acceptable process window and that achieves its respective functional purpose. Historically, the most sensitive features with the smallest margins have determined the margin for all features, although this is not efficient.
Resolution and RET
Due to fundamental inherent limitations in current and near-future optical lithography processes, the layout of the IC is no longer directly equivalent to the pattern printed on the eventual IC wafer. As a result, various RETs are used to compensate for various distortions, or to enable higher resolution, through advanced optical techniques. For background on RETs, see Resolution Enhancement Techniques in Optical Lithography, Chapter 1, by Alfred K. Wong, SPIE Press, 2001; and TCAD Development for Lithography Resolution Enhancement, L. W. Liebmann et al., IBM Journal of Research and Development, Vol. 45, No. 5, September 2001, both of which are incorporated herein by reference in their entirety. RETs are typically added just prior to tape out, and out of view of the designer.
RET features are often ‘sub resolution features’. That is, they are so small in comparison with the lithography system wavelength that they are not singularly resolvable by themselves. These artificial non-printing features serve to improve the resolution and process window of the printing process and typically require a great deal of special care and interpretation when writing or inspecting a photo mask. Their action occurs through beneficial constructive interference with other features in close proximity. The impact of RET features on the fidelity of resolvable IC features is often highly disproportionate to their size.
Similarly, small sub resolution-size defects or positioning errors of circuit features may as well have disproportionately large impact; however the impact is destructive rather than beneficial. Either size or positioning errors may result in very large errors on the patterned substrate, necessitating that mask design and fabrication must be performed with sufficient precision. The “Mask Error Enhancement Factor”, or MEEF, describes a multiplicative factor by which localized mask errors are effectively increased when the mask is printed onto the substrate. MEEF values may be large (>10) for some small features such as contacts or vias necessitating extremely accurate mask printing.
As a result, the patterned feature fidelity and dimensional accuracy are far more difficult to attain as compared to previous generations. These highly non-linear and non-intuitive effects are due to inherent ‘Optical Proximity Effects’ occurring between features in close proximity to one another. This exposes a significant problem impacting the IC industry.
Not only are the critical dimension feature geometries decreasing in size into deep sub-wavelength dimensions but they are also decreasing even faster than the venerated Moore's Law predicts. The already large number of these features is growing at a dramatic rate as well. Furthermore, due to the necessity to mitigate increasingly severe optical proximity effect distortions through resolution enhancement techniques at the mask level, the overall polygonal figure count is skyrocketing at a superlinear rate. As a result, this increased use of RETs dramatically complicates mask fabrication while increasing costs and other complexities.
These critical feature geometries are often written on the photomask with great precision due to circuit sensitivities. These include the sensitivities of performance, power, and other complex parametric and functional yield factors due to lithographic patterned feature dimensional variations. Many structures are extremely sensitive to small variations in the mask due to the severity of the non-linear imaging in this region. As previously discussed, even a moderate mask error enhancement factor, or MEEF, may cause a small error in the mask to be magnified disproportionately and often non-intuitively. This may result in circuit failure. Extreme accuracy may therefore be required. However, not all features have high MEEF and not all features have extreme fidelity needs to achieve the IC's design functional specifications. In fact many features are currently constructed and inspected to much higher accuracy specifications than are actually required, complicating mask fabrication and inspection unnecessarily. However, masks are typically written with uniformly high accuracy such that all features regardless of need or purpose are written with the same precision as those features that actually require the high precision.
These factors have led to increases in the time it takes to create masks, and in the number of errors impacting mask elements, and to the higher costs associated with sub wavelength mask process. Relatively few RET enhancement features are responsible for the great improvements that the technology provides. Many are overused and unneeded corrections and are often applied due to a lack of sophistication of the design, analysis, and fabrication tools currently in use. As a result, while RET is necessary, it can also be problematic needlessly increasing costs without desired functional improvements, and, when non-optimal, may even be responsible for decreasing yield.
Examples
Some of these difficulties may be described by example with respect to a traditional photolithography process, including mask creation and inspection methods, as shown in FIG. 1. At block 102 an integrated chip (IC) design is created, often by using various EDA systems.
The IC digital design flow typically starts with a detailed design specification and an abstract representation of the desired circuit and its operation. This may occur in the form of a computer-based schematic representation of functional units, a logical representation, or a high-level description language which conveys logic state at various times and conditions. Analysis is used at this level to validate that the circuit will perform within design specifications. This abstract description is cast into a physical description during layout synthesis and routing. Physical verification of the layout shapes and projected electrical function is then performed to validate that the physical representation does indeed correspond to the original schematic, or other, representation.
The design 102 often produces a set of circuit elements in a layout to effect a desired circuit electrical operation on a layer-by-layer basis. This is often referred to as the design flow. For background on IC design and mask manufacturing processes, see Resolution Enhancement Techniques in Optical Lithography, Chapter 1, by Alfred K. Wong, SPIE Press, 2001, which is incorporated by reference in its entirety.
Up until tape out or when the design is ready to be handed-off to mask fabrication and manufacturing, a vast amount of information is available including, for example:                the relation of the physical layout features to the design schematic or netlist;        individual circuit element models such as BSIM3 models for Spice circuit simulation,        parasitic extraction data and TCAD-driven model parameters describing detailed properties of various devices and circuits;        various circuit networks of the circuit which may have critical properties such as critical timing or power nets;        manufacturing assumptions which were used in the IC design.        
Furthermore, much of this information is typically organized into a design hierarchy and includes libraries of base cells and other ‘hard IP,’ of pre-designed and pre-characterized blocks.
Tape out of the ‘GDS-II’ layout is typically the last step of 102, and is the hand-off mechanism to manufacturing. Physical circuit elements at the ‘tape out’ level may include, for example, transistors, power buses, resistors, capacitors, and interconnects. However other, necessary but non-circuit, elements may also be included. These include features with various purposes such as descriptive logos to be printed on the IC substrate, non-printing RETs, as well as other printed manufacturing elements such as area fill or slotting features used to respectively improve layer planarity or mitigate the impact of interlayer stresses resulting from dissimilar materials and thermal processing.
However, typically tape out produces a geometries-only design hierarchical data file in GDS-II stream format. The wealth of functional circuit and other design knowledge is eliminated in this step and therefore is unavailable to any data file derived from it or any design, manufacturing, or manufacturing integration activity occurring thereafter.
Process 104 prepares the mask data and creates a job deck. This starts the mask flow, which runs through mask inspection and repair. Knowledge of the mask writing process, and to some extent the photolithography process, may be employed in ‘fracturing’ the GDS-II design during mask data preparation. At ‘fracturing,’ the mask data is prepared for the mask writing equipment by breaking complex polygonal shapes into a simple base set of shapes and by applying mask writer, electron- or laser-spot proximity effect shape, exposure compensation as well as performing biasing, registration mark inserting and other required operations.
Typically, the mask data is prepared into a MEBES, or other low-level machine-specific data file format. The MEBES file holds polygon and geometry information to be used in writing, but like the GDS-II stream file, it holds none of the higher-level IC design or circuit feature functionality or criticality information available in the IC design flow.
There is no ‘knowledge’ of what a feature is beyond its geometry and location. In other words, there is no annotation or linkage to the functional intent of the geometrical feature. Conventionally, very little design from the standpoint of physical layout modification is done at block 104, as the IC design flow sets the layout and often most of the RET and other manufacturing enhancements.
Process 106 writes the mask. Mask writing often involves writing the polygonal shapes and layout of a mask design pattern (from the MEBES file, for example) in a photo- or electron-sensitive coating (often called a “resist”) on a mask substrate (often glass) and then etching in chrome, glass or other materials associated with the specific mask technology being employed (for example CoG, attPSM, altPSM). Mask writing may be based on various technologies, including either electron beam-based or laser-based systems. The fidelity of a mask element written on a mask substrate may be defined by the beam exposure intensity, shaped-beam aperture employed, scan or vector rate, and by the adjacency of other features due to laser, electron, or thermo-chemical proximity effects on the mask. Beneficial effects which may result from additional care such as from increasing the write time with reduced write energy may be offset by the negative effects resulting from thermal and chemical changes in the photoresist caused by other writing events as well as errors due to mechanical or environmental instabilities which occur over longer times. As such, there may be a tradeoff between optimizing writing speed and accuracy.
A mask writing system may be provided with, and controlled by, a database containing the mask's polygonal shape and layout information, such as the mask information in the MEBES data file. However, the design data and ‘design intent’ information usually are not available since it resides in a different database, from which only the geometry information was copied. Design data includes data relating to the electrical net list or schematic, functional intent, and criticality of the various IC circuits and physical elements. Thus, the writing tool only receives simple polygonal shapes and location data. There is no knowledge of the design intention of a given polygon, nor a mechanism for establishing the requisite relationship in order to perform design-aware manufacturing information processing activities capable of enabling the more intelligent mask writing or inspection activities.
In such systems, from this point on, the imaging operations of mask writing and inspection operate under uniform and isotropic imaging assumptions. That is, all features are considered with equal severity and processed under the same conditions as their neighbors, and they are assumed to be spatially and rotationally invariant as well as device- and circuit-unaware. Thus, the polygonal shapes across the mask, regardless of function or real criticality, are treated equally in terms of their importance to the influence on the performance of the resulting circuit.
In continuing reference to the example of a traditional photolithography process as shown in FIG. 1, after mask writing, a mask inspection process 108 is performed. A mask that has been written or printed with polygonal mask elements is inspected for defects. Such inspection often includes comparing a written mask against a reference version of the mask as defined by its mask design database. Defects may include any departures from the reference mask design such as: distortions; missing, misaligned or misshapen shapes; as well as pinholes, bridging features, or holes.
Defects in a mask have generally been assumed to result in defects on the silicon wafer and functional failure in an integrated circuit replicated from that mask. The mask inspection process 108 references only the polygonal shape and layout information from a mask data file 104 generated by the fracturing tool, which is often in a file format such as, for example, Klaris (an abbreviation for KLA-Tencor Reticle Inspection System, produced by KLA-Tencor, Inc. of San Jose, Calif.). Little information relating to the function or relative importance or criticality of individual mask elements can be elicited from the information at hand and from comparing a mask to its mask design template. As a result, each mask element is inspected more-or-less equally in terms of the time and resolution of the inspection system, regardless of its relative importance to the operation of the resulting circuit.
Typically, deviations from the ideal are considered defects. Each found defect is examined, 112, to determine if it can be repaired. If the defect is unrepeatable, an analysis is performed to determine whether it may be accepted without repair. This decision may require advanced modeling and simulation of the defect under the specific lithography process being employed. An “unrepairable defect” might be a defect that cannot be cost-effectively fixed by repair processes such as focused ion-milling or equivalent deposition repair techniques, for example.
An unrepairable defect requires the mask to be discarded and a new mask writing process, 116, to be performed. For example, a mask repair performed by ion beam milling or other processing may be more time-consuming and expensive than writing a new mask. Additionally, mask correction often creates further defects in a mask, as it may add unwanted material during the ion milling process or alternatively may erode the mask elements in some unwanted manner. Merely handling the mask may alter or damage it through any number of means, including electrostatic discharge (ESD). As the costs of mask sets increase into the multi-millions, it is prudent to consider the overall cost, risk, and benefit tradeoffs. At repair block 114, a mask repair process fixes the defect. Mask defect repair often involves focused ion beam (FIB) repair. After the mask correction is performed, the mask inspection process 108 is performed again to find any new defects which may have been introduced during the repair process. Such a cycle is often costly and time-consuming. Once a written mask is found to have either no defects or an acceptable number and type of defects during analysis 110, the integrated chip is created, 118.
During the photolithography process 118, the mask is used to transfer the mask pattern to a wafer. The mask allows light to pass through transparent sections defined by the polygonal mask elements previously written or etched thereon. An image of the mask so produced is then passed through an imaging system often at a reduced image size, and replicated on a wafer surface through the lithography process to create the integrated circuit. Thus, the mask plays a critical role in transmitting the circuit design to the wafer surface.
Despite the amount of care and expense focused on the manufacture of the photomask inherent printing distortions are inevitable due to the nature of subwavelength, or low-k1 lithography. Therefore, there is a need to understand the impact of distortions on the resulting circuit performance. Not all distorted features are damaging to the function of the circuit and application of extreme measures in writing and inspection may be largely ineffective, time consuming and highly costly.
For sub wavelength IC manufacturing the goal is not only to achieve proper circuit function across a practical manufacturing process window despite inherent visual patterning distortions, but to do so with acceptable functional and parametric yield, and within acceptable cost, risk, and schedule constraints. The technique discussed here provides one means in a comprehensive mask and design-aware manufacturing scheme for maximizing the performance and cost effectiveness of sub wavelength mask fabrication through design-awareness.